1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a method of configuring a memory cell array block of a semiconductor memory device, and a method of addressing the memory cell array block.
2. Description of the Related Art
As semiconductor memory devices have increased capacity, memory cell arrays of the semiconductor memory devices have increased accordingly. Therefore, it is very important to divide memory cell arrays into memory cell array blocks of an appropriate size.
When the size of the memory cell array is increased along a word line, a resistance-capacitance (RC) delay may be increased and an area of a decoder may also be increased because an output stage of the decoder for driving the word line needs to have an increased capacity. In addition, power consumption may be increased due to driving of the word line.
When the size of the memory cell array is increased along a bit line, capacitance of the bit line may be increased so that a voltage change of the bit line in a read operation is decreased due to charge sharing, causing difficulty in detecting data accurately. In addition, RC delay may be increased so that a speed of detecting data is decreased. Furthermore, as a length of the bit line is increased, power consumption of a sense amplifier is increased accordingly.
Therefore, to overcome the above-described problems, the memory cell array may be divided into memory cell array blocks of which word lines and bit lines have appropriate lengths, and each of the memory cell array blocks is coupled to an associated peripheral circuit such as a row decoder, a column decoder, a sense amplifier, etc.
However, when the memory cell array is divided into a plurality of memory cell array blocks, the number of required peripheral circuits such as the row decoder, the column decoder and the sense amplifier is increased, resulting in increased chip size. Therefore, the size of the memory cell array block needs to be appropriately determined so as to achieve the smallest possible chip size.
In a conventional memory cell array, the memory cell array block is assigned to a size of a block having a power-of-two number of memory cells. For example, in order to increase the size of a row block including 28 word lines, the size of the row block may be increased to a row block including 29 word lines. This is because there exists a limitation in the bit number of the address for selecting a word line so that the memory cell array block needs to have as many word lines as a corresponding bit number of the address. Similarly, in order to decrease the size of a row block including 29 word lines, the row block can be decreased to a row block including 28 word lines.
FIG. 1 is a block diagram illustrating row blocks of a conventional semiconductor memory device.
Referring to FIG. 1, each of the row blocks 110, 120, 130 and 140 of the conventional semiconductor memory device includes 2K word lines.
FIGS. 2A and 2B are block diagrams illustrating a conventional method of configuring a memory cell array block.
Referring to FIG. 2A, the row blocks 110 and 120 of the row blocks 110, 120, 130 and 140 shown in FIG. 1 are merged into a row block 211, and the remaining row blocks 130 and 140 are merged into a row block 212. Each of the row blocks 211 and 212 is twice the size of each of the row blocks 110, 120, 130 and 140 in FIG. 1.
Referring to FIG. 2B, the row blocks 110, 120, 130 and 140 shown in FIG. 1 are divided into eight row blocks 221, 222, 223, 224, 225, 226, 227 and 228, each of which includes 2K−1 word lines. Each of the row blocks 221, 222, 223, 224, 225, 226, 227 and 228 is half the size of each of the row blocks 110, 120, 130 and 140 in FIG. 1.
As shown in FIGS. 1, 2A and 2B, in order to increase or decrease the size of the memory cell array block, the size of the memory cell array block is necessarily increased or decreased by a power of two according to the conventional art. However, as the memory cell array block includes a plurality of memory cells, adjusting the size of the memory cell array block by a unit of a power of two may not be sufficient to achieve a desired chip size or a desired transmission characteristic of a signal. That is, when the block size is decreased to one half, the chip size may be significantly increased although the transmission characteristic of the signal may be improved, and when the block size is increased to twice itself, the transmission characteristic of the signal may be greatly affected although the chip size may be decreased.